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INTEGRATED CIRCUITS
74ABT161543 74ABTH161543 16-bit latched transceiver with dual enable and master reset (3-State)
Product specification Supersedes data of 1995 Sep 18 IC23 Data Handbook 1998 Feb 27
Philips Semiconductors
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
FEATURES
* Two 8-bit octal transceivers with D-type latch * Live insertion/extraction permitted * Power-up 3-State * Power-up reset * Multiple VCC and GND pins minimize switching noise * Back-to-back registers for storage * Separate controls for data flow in each direction * 74ABTH161543 incorporates Bus hold data inputs which eliminate * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015 * Same function as ABT16543 except for additional Master Reset
control pins and 200V per Machine Model the need for external pull-up resistors to hold unused inputs
DESCRIPTION
The 74ABT161543 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT161543 16-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (nLEAB, nLEBA) and Output Enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control of data transfer in either direction. Master reset (MR) clears all registers simultaneously and sets them Low. The outputs are guaranteed to sink 64mA. Two options are available, 74ABT161543 which does not have the Bus hold feature and 74ABTH161543 which inorporates the Bus hold feature.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ ICCL PARAMETER Propagation delay nAx to nBx Input capacitance I/O capacitance Quiescent su ly current supply CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V Outputs low; VCC = 5.5V TYPICAL 2.5 2.2 3 7 500 9 UNIT ns pF pF A mA
ORDERING INFORMATION
PACKAGES 56-pin plastic SSOP Type III 56-pin plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C ORDER CODE BT161543DL BT161543DGG DRAWING NUMBER SOT371-1 SOT364-1
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT161543 DL 74ABT161543 DGG 74ABTH161543 DL 74ABTH161543 DGG NORTH AMERICA BT161543 DL BT161543 DGG BH161543 DL BH161543 DGG DWG NUMBER SOT371-1 SOT364-1 SOT371-1 SOT364-1
PIN DESCRIPTION
PIN NUMBER 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40,38, 37, 36, 34, 33 1, 56 28, 29 3, 54 26, 31 2, 55 27, 30 4, 25 11, 18, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL 1A0 - 1A7, 2A0 - 2A7 1B0 - 1B7, 2B0 - 2B7 1OEAB, 1OEBA, 2OEAB, 2OEBA 1EAB, 1EBA, 2EAB, 2EBA 1LEAB, 1LEBA, 2LEAB, 2LEBA MRab, MRba GND VCC NAME AND FUNCTION Data inputs/outputs Data inputs/outputs A to B / B to A Output Enable inputs (active-Low) A to B / B to A Enable inputs (active-Low) A to B / B to A Latch Enable inputs (active-Low) Master reset Ground (0V) Positive supply voltage
1998 Feb 27
2
853-1798 19026
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
LOGIC SYMBOL (IEEE/IEC)
4 1 3 2 28 26 27 25 56 54 55 29 31 30
PIN CONFIGURATION
1OEAB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OEBA 1LEBA 1EBA GND 1B0 1B1 VCC 1B2 1B3 1B4 GND 1B5 1B6 1B7 2B0 2B1 2B2 GND 2B3 2B4 2B5 VCC 2B6 2B7 GND 2EBA 2LEBA 2OEBA
MRab 1OEAB 1EAB 1LEAB 2OEAB 2EAB 2LEAB MRba 1OEBA 1EBA 1LEBA 2OEBA 2EBA 2LEBA
R6/R12 2EN4 G2 2C6 8EN10 G8 8C12 R5/R11 1EN3 G1 1C5 7EN9 G7 7C11 3 6D 52
1LEAB 1EAB MRab 1A0 1A1 VCC 1A2 1A3 1A4 GND 1A5 1A6 1A7 2A0 2A1
1A0
5
5D 4
1B0
2A2 GND
1A1 1A2 1A3 1A4 1A5 1A6 1A7 2A0
6 8 9 10 12 13 14 15 9 12D 11D 10
51 49 48 47 45 44 43 42
1B1 1B2 1B3 1B4 1B5 1B6 1B7 2B0
2A3 2A4 2A5 VCC 2A6 2A7 MRba 2EAB 2LEAB
2A1 2A2 2A3 2A4 2A5 2A6 2A7
16 17 19 20 21 23 24
41 40 38 37 36 34 33
2B1 2B2 2B3 2B4 2B5 2B6 2B7
2OEAB
SH00061
SH00060
1998 Feb 27
3
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
LOGIC SYMBOL
FUNCTIONAL DESCRIPTION
The 74ABT161543 contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (nEAB) input and the A-to-B Latch Enable (nLEAB) input are Low the A-to-B path is transparent.
5
6
8
9
10
12
13
14
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 3 54 2 55 1EAB 1EBA 1LEAB 1LEBA MRab 1OEAB 1OEBA MRba 4 1 56 25
A subsequent Low-to-High transition of the nLEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and nOEAB both Low, the 3-State B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs.
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
52
51
49
48
47
45
44
43
15
16
17
19
20
21
23
24
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 26 31 27 30 2EAB 2EBA 2LEAB 2LEBA MRab 2OEAB 2OEBA MRba 4 28 29 25
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
42
41
40
38
37
36
34
33
SH00064
FUNCTION TABLE
INPUTS nOEXX L H X L L L L L L L H= h= L= l= X= = NC= Z= nMRXX L X X H H H H H H H nEXX L X H L L L L L nLEXX X X X L L L L H nAx or nBx X X X h l h l H L X OUTPUTS nBx or nAx L Z Z Z Z H L H L NC Clear Disabled Disabled Disabled + Latch Latch + Display Transparent Hold STATUS
High voltage level High voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA) Low voltage level Low voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA) Don't care Low-to-High transition of nLEXX or nEXX (XX = AB or BA) No change High impedance or "off" state
1998 Feb 27
4
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
LOGIC DIAGRAM
DETAIL A D LE R Q nB0
nA0
Q R
D LE
nA1 nA2 nA3 nA4 nA5 nA6 nA7 MRab nOEBA DETAIL A X 7
nB1 nB2 nB3 nB4 nB5 nB6 nB7
MRba
nOEAB nEBA nEAB
nLEBA
nLEAB
SH00062
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state DC output current output in High state Storage temperature range -64 -65 to 150 mA C VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 UNIT V mA V mA V mA
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Feb 27
5
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER Min 4.5 0 2.0 0.8 -32 64 10 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V C UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH VOL VRST II Input clamp voltage High-level output voltage Low-level output voltage Power-up output voltage3 Input leakage g current Bus Hold current A or B Ports5 74ABTH161543 Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5 5V; VI = GND or 5 5V 5.5V 5.5V VCC = 4.5V; VI = 0.8V VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V IOFF IPU/PD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 74ABT161543 Additional supply current per input pin2 74ABTH161543 Quiescent su ly current supply VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.0V or VCC; VI = GND or VCC; VOE = Don't care VCC = 5.5V; VO = 5.5V; VI = VIL or VIH VCC = 5.5V; VO = 0.0V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 Control pins 35 -75 800 "1.0 "1.0 1.0 -1.0 1.0 -100 0.50 9 0.50 5.0 100 50 50 -50 50 -200 1.5 19 1.5 100 -50 100 50 50 -50 50 -200 1.5 19 1.5 100 A A A A A mA mA mA mA A 2.5 3.0 2.0 3.0 3.6 2.7 0.36 0.13 "0.01 "0 01 0.55 0.55 1.0 1 0 35 -75 A Tamb = +25C TYP MAX -1.2 2.5 3.0 2.0 0.55 0.55 1.0 1 0 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A UNIT
IHOLD
ICC
0.20
1
1
mA
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10% a transition time of up to 100sec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
6
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation delay nAx to nBx, nBx to nAx Propagation delay LEBA to nAx, LEAB to nBx MRba to nAx, MRab to nBx Output enable time OEBA to nAx, OEAB to nBx Output disable time OEBA to nAx, OEAB to nBx Output enable time EBA to nAx, EAB to nBx Output disable time EBA to nAx, EAB to nBx 2 1 2 6 4 5 4 5 4 5 4 5 1.2 1.0 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 1.3 1.3 Tamb = +25oC VCC = +5.0V TYP 2.5 2.2 3.0 2.6 2.6 3.3 3.4 3.5 2.7 3.4 3.5 3.5 2.7 MAX 3.4 2.9 4.1 3.5 3.4 4.4 4.4 4.8 3.5 4.4 4.4 4.4 3.5 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 1.2 1.0 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 1.3 1.3 MAX 3.9 3.5 5.1 4.1 4.2 5.5 5.6 5.4 4.0 5.6 5.7 5.4 4.0 ns ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(L) tw(L) Setup time nAx to LEAB, nBx to LEBA Hold time nAx to LEAB, nBx to LEBA Setup time nAx to EAB, nBx to EBA Hold time nAx to EAB, nBx to EBA Latch enable pulse width, Low MR Pulse width, Low 3 3 3 3 3 6 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 4.0 3.0 TYP -0.3 0.1 -0.1 0.1 -0.1 0.2 -0.1 -0.1 2.0 1.0 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 4.0 3.0 ns ns ns ns ns ns UNIT
1998 Feb 27
7
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
VIN
VM tPHL
VM tPLH VM VM
nOEAB, nOEBA, nEAB, nEBA
VM tPZH
VM tPHZ VOH VOH -0.3V 0V
VOUT
nAx, nBx
VM
SH00040
SH00043
Waveform 1. Propagation Delay For Inverting Output
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
VIN
VM tPLH
VM tPHL
nOEAB, nOEBA, nEAB, nEBA
VM tPZL
VM tPLZ
VOUT
VM
VM nAx, nBx VM VOL +0.3V VOL
SH00041
Waveform 2. Propagation Delay For Non-Inverting Output
SH00044
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
nAx, nBx
nLEAB, nLEBA, nEAB, nEBA
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 3. Data Setup and Hold Times and Latch Enable Pulse Width
1998 Feb 27
EEEEEEEEEE EEE E EEEEEEEEEE EEE E EEEEEEEEEE EEE E
VM VM VM VM ts(H) th(H) ts(L) th(L) VM tw(L) VM
MR
VM
VM tW(L)
tPHL nAx, nBx VM
SH00042 SH00043
Waveform 6. Master Reset Pulse Width, Master Reset to Output Delay
8
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT/H16 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00018
1998 Feb 27
9
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5mm
SOT371-1
1998 Feb 27
10
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Feb 27
11
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable and master reset (3-State)
74ABT161543 74ABTH161543
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03497
Philips Semiconductors
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